1. Field of the Invention
The present invention relates to a vertical nanotube transistor and a process for fabricating the same.
2. Description of the Prior Art
Due to the improvement of techniques for the production of integrated circuits in recent years, the number of semiconductor devices contained on a chip has increased, and the minimum dimensions of a device have become finer for higher integration. Nanometer-scale technology, such as nanotube transistors, has become a focus in industry. Carbon has proven to be the most suitable material for nanoscale devices.
Conventionally, there are two processes for fabricating carbon nanotube transistors (CNT). The first process uses an atomic force microscope (AFM) to force carbon nanotubes onto a substrate on which a gate, source, and drain have been already formed. A carbon nanotube transistor 100 as shown in FIG. 1 is obtained. 110 indicates a source, 120 a drain, 130 a gate, and 140 carbon nanotubes. The carbon nanotube transistor 100 obtained has good transistor properties. However, the formation position of carbon nanotubes cannot be precisely controlled, thus the process is not practical.
The second process includes the following steps. First, an aluminum substrate is subjected to anodic treatment to form nanoscale pores. Next, a catalyst (such as Ni, Fe, or Co) is electroplated on the pore bottom. Next, carbon nanotubes are formed in the pores by chemical vapor deposition (CVD). Next, two ends of the carbon nanotubes formed are connected to different electrodes (serving as source and drain). Finally, an insulating layer is covered and a metal layer is formed to serve as a gate. A carbon nanotube transistor 200 as shown in FIG. 2 is thus formed. In FIG. 2, 210 indicates a source, 220 a drain, 230 a gate, 240 carbon nanotubes, and 250 an insulating layer. However, in the carbon nanotube transistor 200 formed by the above-mentioned process, the gate is not on a plane parallel to a plane on which the source and drain are disposed. The structure is different from ordinary transistors. Therefore, the driving ability of the gate is decreased. In addition, the pores in which nanotubes are formed are defined by anodic treatment of the aluminum substrate. Therefore, the formation position of nanotubes cannot be precisely controlled.
The object of the present invention is to solve the above-mentioned problem and provide a vertical nanotube transistor and a process for fabricating the same, in which the formation position of nanotubes can be precisely controlled.
To achieve the above object, the process for fabricating a vertical nanotube transistor according to the present invention includes the following steps. First, a source layer and a catalyst layer are successively formed on a substrate. A dielectric layer is formed on the catalyst layer and the substrate. Next, the dielectric layer is selectively removed to form a first dielectric mesa on the catalyst layer, a gate dielectric layer on the substrate to align with a sidewall of the catalyst layer and the first metal layer, and a second dielectric mesa on the substrate. The first dielectric mesa and the gate dielectric layer are spaced apart by a first opening, and the gate dielectric layer and the second dielectric mesa are spaced apart by a second opening. Next, a nanotube layer is formed in the first opening. Finally, a drain layer is formed on the nanotube layer and the first dielectric mesa and a gate layer is formed in the second opening.
The vertical nanotube transistor of the present invention includes a source layer formed on a substrate; a catalyst layer formed on the source layer; a first dielectric mesa on the catalyst layer; a gate dielectric layer on the substrate to align with a sidewall of the catalyst layer and the source layer and spaced apart from the first dielectric mesa by a first opening; a second dielectric mesa on the substrate and spaced apart from the gate dielectric layer by a second opening; a nanotube layer formed in the first opening; a drain layer on the nanotube layer and the first dielectric mesa; and a gate layer in the second opening.